STLC1502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
Error Cases
• BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt if ITE is set.
• AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with
an interrupt if the ITE bit is set. To resume, set the START or STOP bit.
• ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an
interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is
cleared).
Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possi-
ble «0» bits transmitted last. It is then necessary to release both lines by software.
Event Flags and interrupt generation diagram
7.6.4 I2C registers map [0X0C300000]
The base address of the Remap & Pause register is 0x0C300000.
The offset of any particular register from the base address is the following.
Address
I2C_regBase+ 0x20
I2C_regBase+ 0x24
I2C_regBase+ 0x28
Register
Name
I2CCR
I2CSR1
I2CSR2
R/W Notes
R/W I2C configuration register
R/W I2C status register 1
R/W I2C status register 2.
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