STLC1502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
• The SDA/SCL lines are released after the transfer of the current byte.
7.6.3.2 Master Mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL
bit set) and generates a Start condition. Once the Start condition is sent:
– The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave
address, holding the SCL line low.
Slave address transmission
The slave address is then sent to the SDA line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence causes the following
event:
– The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the
SCL line low. The second address byte is then sent by the interface. After completion of this transfer (and
acknowledge from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register (for example
set PE bit), holding the SCL line low. Next the master must enter Receiver or Transmitter mode.
Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a
repeated Start condition and resend the header sequence with the least significant bit set (11110xx1).
Master Receiver
After the address transmission and SR1 and CR registers have been accessed, the master receives
bytes from the SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVFand BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the
SCL line low. To close the communication: before reading the last byte from the DR register, set the
STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must
be cleared just before reading the second last data byte.
Master Transmitter
After the address transmission and SR1 register has been read, the master sends bytes from the DR
register to the SDA line via the internal shift register. The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the SCL line low. When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to generate
the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).
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