STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
STLC4420A
Figure 17. AHB bus timing
Serial host interface
4.4
The read data is registered on the 15 SPI_CLK of the address phase. SPI_CSX high time
must be 20ABClocks - 15SPI_CLKs. If ABClock period is 100ns (10 MHz) and SPI_CLK
period is 40ns then the time between writing DMA write address register and reading the
DMA data register is (20 * 100) - (15 * 40) = 1.4us. If the ABClock period is 25ns (40 MHz)
then SPI_CSX high time is < 0 for Read data to be valid. In this case, only the Min High time
for SPI_CSX must be observed.
Host registers
The Host can access the registers listed in Table 5.
Table 5. Host registers
Domain
A14-A8 Access
X00 0000
SPI_CLK
RW
X00 0010
ARM
X00 0100
R
X00 0110
ARM
X00 1000
R
X00 1010
X00 1100
SPI_CLK
RW
X00 1110
X01 0000
SPI_CLK
W
X01 0010
Shared
Shared
X01 0100
RW
X01 0110
X01 1000
RW
X01 1010
Host
X10 0100
RW
X10 0110
Host
X10 1000 RW
Shared
X10 1100 RW
Sleep access
RW
--
--
RW
--
--
--
RW
--
--
Description
ARM interrupt
ARM interrupt
enable
Host interrupt
Host interrupt
enable
Host interrupt
acknowledge
GP1
communication
GP2
communication
Device control/
status
DMA data
DMA write
control
Notes
(1), (2)
(1)
(1), (2)
25/40
Share Link: 
