STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
STLC4420A
Registers description
Table 8. ARM interrupt acknowledge (continued)
Bit position
Name
Description
27:16
Reserved
Not Implemented
15:0
HOSTMSG
General purpose Host Message Interrupts. May be written by the
Host to cause an interrupt to the ARM processor.
5.3
ARM interrupt enable
The ARM processor writes this register, and enables interrupts from the ARM interrupt
register. An interrupt is generated when corresponding bits in both the ARM interrupt
register and the ARM interrupt enable register are both logic 1.
The format of the register is defined in Table 9.
Table 9. ARM interrupt enable
Bit position
Name
Description
31
ARM_ASLEEP
Indicates that an access to hardware registers or device memory
(by Host) was attempted while the device was in sleep-mode.
30
DMA WR done Last Write Occurred
29
DMA RD done Last Read Occurred
28
27:16
DMA RD ready DMA rd FIFO ready to be read
Reserved
Not Implemented
15:0
HOSTMSG
General purpose Host Message Interrupts. Written by the ARM
to enable Interrupt on selected bit(s)
5.4
Host interrupt register
The bits of this register reflect the Host interrupt register with the masking by the host
interrupt enable register. This register can be written or read while the device is in sleep
mode (for example, running off the low frequency oscillator) and not generate an
ARM_asleep interrupt.
The format of the register is defined in Table 10.
Table 10. Host interrupt register
Bit position
Name
Description
31
ARM_ASLEEP
Indicates that an access to hardware registers or device memory
(by Host) was attempted while the device was in sleep-mode.
30
DMA wr done Last Write Occurred
29
DMA rd done Last Read Occurred
28
DMA rd ready DMA rd FIFO ready to be read
27
NotSleep
Not Implemented
31/40
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