STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
Registers description
STLC4420A
Table 13. Device control/status register
Bit number
Name
Description
16
HostRes
Host Reset flag - A logic 1 indicates that the previous
reset was generated by the Host asserting the HostReset
bit in this register.
15
SleepMode
14:6
ClockDivisor
SleepMode flag - A logic 1 indicates that the device is in
Sleep Mode, i.e. running off the low frequency oscillator.
(Read Only)
The clock divisor setting on the PMU clock control register
(Read Only)
5
Reserved
Not Implemented
When asserted, SerHost mode is updated by bits 3:0
4
UseSerHostOverRide
1 = Update SerHost mode based on bits 3:0
0 = No change to SerHost mode
Number of wait states between Address and Data phase
in 3_Wire mode 0 = Zero wait states between Address
and Data phase in 3_Wire mode 1 = One wait state
between Address and Data phase in 3_Wire mode
3
Host_3_WireAdrDataWait
Read value is currently selected 3_ WireAdrDataWait.
May be different that last written value when
UseSerHostOverRide is deasserted.
Select 3 wire mode using SPI_DIN for Serial data input
and output 0 = Use 4 wire mode, SPI_DIN input only and
SPI_DOUT output only 1 = Use 3 wire mode, SPI_DIN for
input and output
2
Host_3_WireMode
Read value is currently selected 3_ WireMode. May be
different that last written value when
UseSerHostOverRide is deasserted
Shift SPI_DIN and SPI_DOUT by 1 clock phase 0 = No
phase shift 1 = Phase shift SPI_DIN and SPI_DOUT by 1
clock phase
1
Host_PhaseShift
Read value is currently selected PhaseShift. May be
different that last written value when
UseSerHostOverRide is deasserted
Select active edge of SPI_CLK 0 = Rising edge of
SPI_CLK is active edge
1 = Falling edge of SPI_CLK is active edge
0
Host_InvertClock
Read value is currently selected InvertClock. May be
different that last written value when
UseSerHostOverRide is deasserted
34/40
Share Link: 
