STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
Registers description
STLC4420A
5.11
DMA write length register
This 16 bit register is programmed with the maximum byte count of the next DMA Write
transfer. Only the low-order 16 bits are used. The value programmed can be any number of
bytes from 1 to 65535.
The format of the register is defined in Table 16.
Table 16. DMA write length register
Bit number
Name
Description
31:16
Reserved
15:0
Data length
Maximum byte count
5.12
DMA write base address register
The DMA Write Base Address is written to point to the first location for the DMA Data
register write in the Devices AHB space. The address will be incremented after every Host
access to the Data register. There is no restriction on the Base Address. Byte, Half-word,
Word and QuadWord addresses are supported.
The format of the register is defined in Table 17.
Table 17. DMA write base address register
Bit number
Name
Description
31:0
DMA Write Base
Address for 1st DMA write
5.13
DMA read control register
The DMA Read Control register allows the ARM or the Host to enable the DMA Read
channel. Only the ARM can modify the HostAllowed bit. When the HostAllowed bit is de-
asserted the Host is not allowed to write the DMA Read Control, Length or Base registers.
Only bits 15:0 are accessible by the Host.
The format of the register is defined in Table 18.
Table 18. DMA read control register
Bit number
Name
Description
31:8
Reserved
7
HostAllowed
When bit is set, the Host is allowed to write to DMA Read
Control, Length and Base registers. HostAllowed bit is
only writable by the ARM. HostAllowed default value is '1'.
'0' = Host not Allowed to write Control, Length and Base
registers. '1' = Host IS Allowed to write Control, Length
and Base registers.
6:1
Reserved
0
Enable
Specifies the access direction
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