STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
STLC4420A
Registers description
Table 12. Host interrupt acknowledge register
Bit position
Name
Description
27:16
Reserved
Not implemented
15:0
HOSTMSG
General purpose host message interrupts. Written by the ARM
to enable Interrupt on selected bit(s)
5.7
5.8
General purpose 1 and 2 communication registers
These 32-bit general-purpose register can be written or read by either the Host or the ARM
processor.
Device control/status register
The device control/status register is used by the Host to configure the device by writing to
bits 31:27. The status of the device is visible to the Host by reading bits 22:6.
The contents of the register are defined in Table 13.
Table 13. Device control/status register
Bit number
Name
Description
31
SetHostOverride
When set, tells processor to use boot options set by bits
30 and 29 and override boot strapping options after reset.
30
SetStartHalted
29
SetRAMBoot
When bit 31 is set, this bit forces CPU to remain idle when
reset is de-asserted. (Read/Write)
When bit 31 is set, processor boots from RAM. Over-rides
TMSEL strapping options (Read/Write)
28
SetHostReset
When set, produces an active high(1) reset level to the
ARM (Read/Write) Must be cleared to de-assert(0) reset.
27
SetHostCPUEn
Enables processor after StartHalted has been asserted.
(Read/Write)
26:23
Reserved
Not Implemented
22
StartHalted
Indicates that the processor clock was stopped after the
previous reset. (Read Only)
21
RestartAsserted
Indicates that OSC Restart is asserted. (Read Only)
20
Reserved
Not Implemented
19
SoftRes
18
RTCRes
Soft Reset flag - A logic 1 indicates that the previous reset
was generated by a write to the PMU system control
register bit 0.
RTC Reset flag - A logic 1 indicates that the previous
reset was generated by the Real Time Clock.
17
HardRes
Hard Reset flag - A logic 1 indicates that the previous
reset was generated by asserting the RESET_N pin.
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