STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
Registers description
STLC4420A
Table 10. Host interrupt register
Bit position
Name
Description
26:16
Reserved
Not Implemented
15:0
ARMMSG
General purpose Host Message Interrupts. Written by the ARM
to enable Interrupt on selected bit(s)
5.5
Host interrupt enable register
The Host writes this 32-bit register to enable interrupts from the host interrupt register. A
Host interrupt is generated if the corresponding bit in both the host interrupt register and the
host interrupt enable register are both active.
The format of the register is defined in Table 11.
Table 11. Host interrupt enable register
Bit position
Name
Description
31
ARM_ASLEEP
Indicates that an access to hardware registers or device memory
(by Host) was attempted while the device was in sleep-mode.
30
DMA wr done
29
DMA rd done
28
DMA rd ready
27
NotSleep
26:16
Reserved
Not Implemented
15:0
HOSTMSG
General purpose ARM Message Interrupts. Written by the ARM
to cause an interrupt to the HOST
5.6
Host interrupt acknowledge register
This 32-bit register is written by the Host, and clears interrupts in the Host Interrupt Register.
Writing a logic 1 in any bit position cause the corresponding interrupt bit to be cleared. All
other bits are unaffected.
The format of the register is defined in Table 12.
Table 12. Host interrupt acknowledge register
Bit position
Name
Description
31
ARM_ASLEEP
Indicates that an access to hardware registers or device memory
(by Host) was attempted while the device was in sleep-mode.
30
DMA WR done Last write occurred
29
DMA RD done Last read occurred
28
DMA RD ready DMA RD FIFO ready to be read
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