STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
Serial host interface
STLC4420A
Table 5. Host registers (continued)
Domain
A14-A8 Access Sleep access
Description
Notes
Shared
Shared
X10 1110 RW
X11 0000
RW
X11 0010
--
DMA write length
--
DMA write base
Shared
Shared
Shared
X11 0100 RW
X11 0110 RW
X11 1000
RW
X11 1010
--
DMA read
control
--
DMA read length
--
DMA read base
1. Readable during Sleep Mode without generating Sleep interrupt. All registers are readable during
Sleep Mode. Reading registers not marked as Readable during Sleep will set the ArmAsleep bit in
the Host and ARM Interrupt registers.
2. Writable during Sleep Mode. All registers are writable during Sleep mode. Writing registers not
marked as writable during Sleep mode requires several 32 kHz clock cycles to complete the write
access and will set the ArmAsleep bit in the Host and Arm Interrupt.
The Host accesses each register as a 16-bit register. Registers which are physically 32-bits
have 2 addresses in the Host address space. The even address (A9 == 0) is the low 16-bits
and the odd address (A9 == 1) is the high 16-bits.
A15 is the read bit. A15 is set for reads and cleared for Writes. For example, to write ARM
Interrupt[31:16] address bits 15:0 are set to 16'h0100. Address bits 15:0 are set to 16'h8100
to read ARM Interrupt[31:16]. A7 - A0 are don't care bits and can be set to any value by the
Host. It is required that a full 16-bit address be sent. The initial data phase does not begin
until the 16-bit address phase has completed.
4.5
Host writes
The Host writes to a 16-bit register by sending a 16 bit Address phase with A15 set to zero.
The Address phase is followed by a 16-bit data phase. D15 is the first bit of data phase and
D0 is the last bit of the data phase. D15 - D0 are written to the selected register on the active
edge of SPI_CLK when D0 is present on SPI_DIN.
When the register is in the ARM or Shared clock domain the write process begins when on
the active edge of SPI_CLK when D0 is present on SPI_DIN. The write completes after the
data is synchronized into the ABClock domain. This process takes 3 ABClock cycles.
ABClocks are 30us each in Sleep mode! Host must ensure 90us delays between writes to
non-Sleep accessible registers when device is in Sleep mode.
If less than 16 bits are written during the data phase the data is not written to the addressed
register. The SPI_CLK may stop at any time. The current phase (address or data) is not
interrupted by a stopped (or slowed) SPI_CLK. The logic remains in the current phase until
SPI_CLK resumes or SPI_CSX is de-asserted.
26/40
Share Link: 
