STLC4420A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC4420A' PDF : 40 Pages View PDF
Registers description
5
Registers description
STLC4420A
5.1
Note:
ARM interrupt register
The HOSTMSG bits of this register are written by the Host and generate interrupts to the
ARM processor when the corresponding bit is set in the ARM Interrupt Enable register.
Writing a logic 1 causes the corresponding interrupt bit to be set. All other bits are
unaffected; previously set bits will remain set. This register can be read/written while the
device is in sleep Mode (i.e. running off the low frequency oscillator) and not generate an
ARM_asleep interrupt.
Both the ARM and Host Interrupt Register have the bit "ARM_ASLEEP". Although only the
host generates this bit it is used as an interrupt source to both. When the Host sees this
interrupt, it is expected that it will poll the device control/status Register until the SleepMode
status bit is de-asserted by ARM before continuing.
The format of the register is defined in Table 7.
Table 7. ARM interrupt register
Bit position
Name
Description
31
ARM_ASLEEP
Indicates that an access to hardware registers or device memory
(by Host) was attempted while the device was in sleep-mode.
30
DMA wr done Last Write Occurred
29
DMA rd done Last Read Occurred
28
27:16
DMA rd ready DMA rd FIFO ready to be read
Reserved
Not Implemented
15:0
HOSTMSG
General purpose Host Message Interrupts. May be written by
the Host to cause an interrupt to the ARM Processor.
5.2
ARM interrupt acknowledge
This register is written by the ARM processor and clears bits in the ARM interrupt register.
Writing a logic 1 in any bit position causes the corresponding interrupt bit to be cleared. All
other bits are unaffected.
The format of the register is defined in Table 8.
Table 8. ARM interrupt acknowledge
Bit position
Name
Description
31
ARM_ASLEEP
Indicates that an access to hardware registers or device memory
(by Host) was attempted while the device was in sleep-mode.
30
DMA wr done Last Write Occurred
29
DMA rd done Last Read Occurred
28
DMA rd ready DMA rd FIFO ready to be read
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