Figure 18. DRAM Read Cycle
DRA
(8:0)
ROW ADDR. 1
COLUMN ADDR. 1 COLUMN ADDR. 2
TDA7503
ROW ADDR. 2
RAS
CAS
DRD
DRD
(3:0)
Figure 19. DRAM Write Cycle
DRA
(8:0)
ROW ADDR. 1
NIBBLE 1
NIBBLE 2
D02AU1389
COLUMN ADDR. 1 COLUMN ADDR. 2
ROW ADDR. 2
RAS
CAS
DWR
DRD
(3:0)
NIBBLE 1
NIBBLE 2
D02AU1390
FUNCTIONAL DESCRIPTION.
The Aladdin IC broken up into two distinct blocks. One block contains the two DSP Cores and their associated
peripherals. The other contains the MX51 Core and its associated peripherals. The interface between the two
blocks is the Host Interface.
24-BIT DSP CORE.
The two DSP cores are used to process the converted analog audio data coming from the CODEC chip via the
SAI and return it for analog conversion. Functions such as volume, tone, balance, and fader control, as well as
spatial enhancement and general purpose signal processing may be performed by the DSPs.
Some capabilities of the DSPs are listed below:
– Single cycle multiply and accumulate with convergent rounding and condition code generation
– 2 x 56-bit Accumulators
– Double precision multiply
– Scaling and saturation arithmetic
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