TDA7503 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7503' PDF : 30 Pages View PDF
TDA7503
Micro Memory Interface
The MX51 core requires an external memory interface to connect to external program memory and memory
mapped peripherals. This is implemented like the standard 80C51 Port 2/Port 0 Multiplexed 16 Bit Address/8
Bit Data Bus. The signals RD, WR, XPSEN, and XALE will also be output. The External Memory Interface must
also have circuitry to program the external EPROM (or any non-volatile memory) in-circuit. This means that the
normal operation of the external memory interface must be altered to handle the program timing of the EPROM.
By treating the Port 2/Port 0 pins as GPIO the programming can be achieved in software. When this mode is
entered instruction execution is switched to internal AUX-RAM.
Serial Peripheral Interface
The MX51 core requires a serial interface to receive commands and data over the LAN. During an SPI transfer,
data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the
information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. The
SS Pin will act as a GPIO when the SPI is in master mode or the SPI is disabled.
When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simulta-
neously shifted in a second data pin. The central element in the SPI system is the shift register and the read
data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction.
Control Interface
The MX51 requires a set of external general purpose input/output lines, two external interrupt lines, and a reset
line. These signals are used by external devices to signal events to the MX51. The GPIO lines are implemented
as the MX51's Port 1 GPIO. The two external interrupts are connected to the INT0 and INT1 lines on the micro.
The RESET pin is used to reset the micro.
PLL Clock Oscillator
The PLL Clock Oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator
when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock
input and a multiply block MF (33 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock
by a ratio MF/IDF to generate the internal clock. It is recommended that the input clock is not divided down to
less than 4 MHz as this reduces the Phase Detector's update rate.
The clocks to the DSP and the MX51 can be selected to be either the VCO output divided by 2 or 4 respectively,
or be driven by the XTI pin directly.
The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting bit 1 of the
PCON Register).
MX051 Interrupts
The MX051 Core provides for 5 interrupt sources, INT1, INT0, TIMER1, TIMER0, and SERIAL Data. There ex-
ists a corresponding Interrupt Enable register and Interrupt Priority Register.
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