TDA7503 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7503' PDF : 30 Pages View PDF
TDA7503
– 48-bit or 2 x 24-bit parallel moves
– 64 interrupt vector locations
– Fast or long interrupts possible
– Programmable interrupt priorities and masking
– Repeat instruction and zero overhead DO loops
– Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines
– Bit manipulation instructions possible on all registers and memory locations. Also Jump on bit test.
– 4 pin serial debug interface
– Debug access to all internal registers, buses and memory locations
– 5 word deep program address history FIFO
– Hardware and software breakpoints for both program and data memory accesses
– Debug Single stepping, Instruction injection and Disassembly of program memory
DSP PERIPHERALS
There are a number of peripherals that are tightly coupled to the two DSP Cores. Except for the memories and
the Host Interface, a single peripheral is multiplexed to both of the DSP Cores. In the case of the Host Inter-
face(HI), for DSP to Micro communication, there are two identical peripheral blocks providing the same function
to both DSP Cores. Each of the peripherals are listed below and described in the following sections.
– 512 x 24-Bit X-RAM.
– 512 x 24-Bit Y-RAM.
– 1024 x 24-Bit Program RAM (5632 x 24 for DSP1)
– 256 x 24-Bit Data X-ROM.
– 256 x 24-Bit Data Y-ROM.
– 128 x 24-Bit Boot ROM.
– Serial Audio Interface (SAI) multiplexed to both DSPs.
– Synchronous Serial Interface (SSI) multiplexed to both DSPs.
– XCHG Interface for DSP to DSP communication.
– Host Interface (HI) for DSP to Micro communication.
– External Memory Interface (DRAM/SRAM) multiplexed to both DSPs for time-delay.
– Single Debug Port multiplexed to both DSPs.
– Cordic Arithmetic Unit
DATA AND PROGRAM MEMORY
Both DSP0 and DSP1 have an identical set of Data and Program memories attached them. Each of the mem-
ories are described below and it is implied that there are two of each type, one set connected to DSP0 and the
other to DSP1. The only exception is the case of the P-RAM where DSP0 has a 1024 x 24-Bit PRAM and DSP1
has a 5632 x 24-Bit PRAM.
512 x 24-Bit X-RAM (XRAM)
This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is
generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be written
to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch so
that it can be routed to and from all peripheral blocks.
512 x 24 Bit Y-RAM (YRAM)
This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is gener-
ated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from
the Data ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be
routed to and from other blocks.
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