TDA7503 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7503' PDF : 30 Pages View PDF
TDA7503
1024 x 24-Bit Program RAM (PRAM 5632 x 24-bit for DSP1)
This is a 1024 x 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Ad-
dress, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching,
and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Pro-
gram Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the
PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding.
256 x 24-Bit X-ROM (XROM)
This is a 256 x 24-Bit factory programmed X-ROM. The 16-Bit address, XABx(15:0) is generated by the AGU
Unit. The 24-Bit Data is multiplexed onto the XDBx Bus when the address is valid.
256 x 24-Bit Y-ROM (YROM)
This is a 256 x 24-Bit factory programmed Y-ROM. The 16-Bit address, YABx(15:0) is generated by the AGU
Unit. The 24-Bit Data is multiplexed onto the YDBx Bus when the address is valid.
128 x 24-Bit Bootstrap ROM (PROM)
This is a 128 x 24-Bit factory programmed Boot ROM used for storing the program sequence for initializing the
DSP. Essentially this consists of a routine that is called when the MX51 requests that a DSP image be sent via
the Host Interface. It is the task of the Boot code to read the data being sent by the micro from the Host Interface
FIFO and store it in PRAM, XRAM, YRAM, and/or external DRAM.
Operating Mode Register
The operating mode register contains one bit to choose between boot mode (always from the Host Interface) or
normal mode (execution from PRAM). This bit will be set when the DSP is reset (by writing to the RSDSPx bit
in the CLKCNTL register). It must be cleared by the boot code to enable execution from PRAM.
DSP Memory Maps
The DSP memory Maps are shown in Figure 26.
Serial Audio Interface (SAI)
The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it
can be returned through this interface. There is only one SAI on the chip that can be accessed by either DSP.
The features of the SAI are listed below.
– Five Synchronized Stereo Data Transmission Lines
– Four Synchronized Stereo Data Reception Lines
– Slave operating mode, clock lines can be Master and both input and output
– Transmit and Receive Interrupt Logic triggers on Left/Right data pairs
– Receive and Transmit Data Registers have two locations to hold left and right data.
Synchronous Serial Interface (SSI)
The SSI is used for communication with devices with a conventional serial interface (not I2S stereo serial audio
interface). The SSI shares some pins with the SAI. When the SSI is activated, some of the SAI pins are switched
from the SAI to the SSI. The SAI and SSI can operate in parallel.
The features of the SSI are listed below.
– Slave operating mode, FSYNC and SSISCK are inputs.
– Data sizes of 8, 16, and 24 bits are supported.
– Frame Sync (FSYNC) and SCK (SSISCK) signals connected to both the receiver and transmitter.
– Normal mode or Network mode possible.
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