TDA7503 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7503' PDF : 30 Pages View PDF
TDA7503
XCHG Interface (DSP to DSP Exchange Interface)
The Exchange Interface peripheral provides bidirectional communication between DSP0 and DSP1. Both 24 bit
word data and four bit Flag data can be exchanged. A FIFO is utilized for received data. It minimizes the number
of times an Exchange Interrupt Service Routine would have to be called if multi-word blocks of data were to be
received. The Transmit FIFO is in effect the Receive FIFO of the other DSP and is written directly by the trans-
mitting DSP. The features of the XCHG are listed below.
– 10 Word XCHG Receive FIFO on both DSPs
– Four Flags for each XCHG for DSP to DSP signaling
– Condition flags can optionally trigger interrupts on both DSPs
Figure 20. DSP1 and DSP0 Memory Spaces
BOOT-SPACE
P-SPACE
X-SPACE
SFFFF PERIPHERALS
SFFC0
Y-SPACE
BOOT-SPACE
P-SPACE
X-SPACE
SFFFF PERIPHERALS
SFFC0
Y-SPACE
S03FF
S007F Boot-ROM
S0000
S02FF
S0200
S01FF
P-RAM
X-ROM
X-RAM
DSP0
Y-ROM
Y-RAM
S15FF
P-RAM
S007F Boot-ROM
S0000
S02FF
S0200
S01FF
X-ROM
X-RAM
DSP1
Y-ROM
Y-RAM
D01AU1317
Host Interface(HI)
The MX51 communicates with the DSPs through the Host Interface. There is a separate HI for each of the
DSPs. Two Host Interfaces are included. HI0 for Host to DSP0 communication, and HI1 for Host to DSP1 com-
munication. The features of the HI are listed below.
– 8 Word Host Receive FIFO - DSP Side
– 4 Word Host Receive FIFO - Host (MX51) Side
– Two Flags for each HI for DSP to Host signaling (can optionally trigger interrupts)
– Command Vector Register allows Host to trigger any DSP vectored interrupt
DRAM/SRAM Interface (EMI)
The External DRAM/SRAM Interface is viewed as a memory mapped peripheral. Data transfers are performed
by moving data into/from data registers and the control is exercised by polling status flags in the control/status
register or by servicing interrupts. An external memory write is executed by writing data into the EMI Data Write
Register. An external memory read operation is executed by either writing to the offset register or reading the
EMI Data Read Register, depending on the configuration.
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