VG4616321B View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG4616321B' PDF : 82 Pages View PDF
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of tCK and tRC. Input signals are changed one time during tCK. Assume that there are only one read/write
cycle during tRC (min).
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle tCCD (min).
6. Power-up sequence is described in Note 11.
7. A.C. Test Conditions
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
3.0V / 0.0V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
Output
30pF
3.3V
1.2KΩ
870Ω
Output
ZO=50Ω
1.4V
50Ω
30pF
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
Document:1G5-0145
Rev.1
Page 24
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