VG4616321B View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG4616321B' PDF : 82 Pages View PDF
VIS
SSTL_3 Interface
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Reference Level of Output Signals (VREF)
Output Load
Input Signal Levels
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals(VREF)
0.45*VDDQ
Reference to the Under Output Load
VREF + 0.4/VREF-0.4
1ns
0.45*VDDQ
AC Test Load Circuits (for SSTL - 3 interface) :
VDDQ
VREF
VDDQ
0.45 * VDDQ
VOUT
RS = 25 Ohms
VTT = 0.45 * VDDQ
RT2 = 50 Ohms
VIN
Z = 50 Ohms
Device
Under
Test
RT1 = 50 Ohms
VTT = 0.45 * VDDQ
CLOAD = 30 pF
VREF = 0.45 * VDD
VSS
SSTL-3 A.C. Test Load
8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns).
9. tOHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number)
Document:1G5-0145
Rev.1
Page 25
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