
VIS
Preliminary
Figure 4. Power on Sequence and Auto Refresh (CBR)
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
CKE
CS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
High level
is required
Minimum of 8 Refresh cycles are required
2 Clock min.
RAS
CAS
WE
DSF
BS
A9
A0 ~ A8
DQM
t
RP
DQ
Hi-Z
Precharge All
Command
Inputs must be
1st Auto Refresh
Command
stable for 200 us
Address Key
t
RC
2nd Auto Refresh
Command
Mode Register Any
Set Command Command
Document:1G5-0145
Rev.1
Page 30