VV5801C001 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV5801C001' PDF : 23 Pages View PDF
VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
memory. This scheme is illustrated below:
Reset[n]
Read[n]
Shutter
Vpix
VBlack
VRT
VVRDeasrke1t
Exposure
y VWhite
r Read 1
Read 2
Not to scale
Read 3
ina Figure 5.7 : Multiple dark frame periods explanation
Vim
VDark2
Prelim
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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
6. The Control Register & Serial Communication
The VV6801 includes a full duplex serial interface, and can be controlled and configured by a host processor.
Data describing the current configuration of the camera is stored in a 20-bit control register. This register can
be read from the camera on the serial interface, and can also be written to from the serial interface to change
camera operation.
6.1 General description
When a 22-bit serial interface data word arrives at the camera on DIN, the first 20 (msb) bits are loaded into
a shift register, and the last two bits (‘R/W’) are examined to ascertain if a ‘read’ operation or a ‘write’
operation is required. If a ‘write’ is required (‘R/W’ = “00”) the contents of the input shift register are transferred
to the control register. Otherwise, the current contents of the control register is output on DOUT. (Note: In
‘test mode’, that is with CR[7..5]>0, certain other signals are monitored by DOUT and CR[19..0] is not
transmitted.)
y The signals used to effect the serial data interface are:
• DINSerial Data In; DIN is sampled on the rising edge of DCK
r • DOUTSerial Data Output
a • DCKSerial Data Clock
• DLATSerial Data Latch; transfers the input data word to the control register (for ‘write’),
in and initiates control register output on DOUT (for CR[7..5]=0)
DIN
DCK
DLAT
lim R/W
Pre&
20
20-bit Shift Register
20
Control Register CR[19..0]
8 to 1 Multiplexer
DOUT
20
3 CR[7:5]
CR[19..0]
Figure 6.1 : Control register block diagram
6.2 Serial Communication Protocol
The host must perform the role of a communications master, while the camera acts as a slave receiver and
transmitter. Communication from host to camera takes the form of a 22-bit data word, with a 20-bit data word
returned to the host. Since the serial clock (DCK, maximum frequency 100kHz,) is generated by the host, the
host determines the data transfer rate.
The host sends the 20 bit control word, most significant bit first, then either holds DIN high for two clock
cycles, to indicate a ‘read’, or holds DIN low for two clock cycles, to indicate a ‘write’. The host also takes
DLAT high for one clock cycle, corresponding to the last bit of the R/W pair. This defines the end of the
transfer and latches the data word to the Control Register, if required (R/W=00). DLAT also (on the next rising
edge of DCK) transfers the contents of the Control Register to the Shift Register, which is then output to
DOUT if CR[7..5] = 0.
The data transfer protocol is illustrated below:
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