XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
Preliminary
XR16C872
may want to stop it. The UART resumes normal
operation when a RX character’s start bit is detected,
a change of state on any of the modem input pins RX,
RI#, CTS#, DSR#, CD#, or transmit data is loaded into
the FIFO by the user. It typically takes 30us for the
crystal oscillator to restart from sleep mode depending
on the crystal properties. This delay must be taken into
consideration during design as receive character(s)
may be lost. The number of characters lost depends on
the operating data rate, more at higher data rate. If the
sleep mode is enabled and the UART is awakened by
one of the conditions described above, it will return to
the sleep mode automatically after the last character is
transmitted or read by the user and no interrupt pend-
ing. The chip will not enter sleep mode while an
interrupt(s) is still pending and the oscillator would still
be running. The UART stays in the sleep mode of
operation until it is disabled by setting IER bit-4 to logic 0.
Example of Sleep mode enable during initialization:
Write LCR with 0xBF
Set EFR bit-4 to logic 1
Write LCR with Op.value
Set IER bit-4 to logic 1
; access to EFR registers
; enable non-550 functions
; in IER, EFR and MCR registers
; point to basic registers
; set sleep mode
; service all pending interrupts
; no modem port activity
; enters sleep mode and stop
; the oscillator
For lowest sleep current the following pins should idle
at logic 1 state: RX A/B should be at logic 1 and data bus
should be pull-down with ~47K resistors if the control-
ler puts the data bus in tri-state condition. No input pins
should be left floating.
Loopback Mode
The internal loopback capability allows on board diag-
nostics. In this mode, the normal modem interface pins
are disconnected and re-configured for loopback inter-
nally. MSR bits 4-7 are also disconnected. However,
MCR register bits 0-3 can be used for controlling
loopback diagnostic testing. In this mode, OP1 and
OP2 in the MCR register (bits 0-1) control the modem
RI# and CD# inputs respectively. MCR signals DTR#
and RTS# (bits 0-1) are used to control the modem
CTS# and DSR# inputs respectively. The transmitter
output (TX) and the receiver input (RX) are discon-
nected from their associated interface pins, and in-
stead are connected together internally (See Figure 7).
The CTS#, DSR#, CD#, and RI# are disconnected from
their normal modem control inputs pins, and instead
are connected internally to DTR#, RTS#, OP1# and
OP2#. Loopback test data enters transmit holding
register via the user data bus interface, D0-D7. The
transmitter serializes the data and passes the serial
data to the receive UART via the internal loopback
connection. The receive UART converts the serial data
back into parallel data that is then made available at the
user data interface, D0-D7. The user optionally com-
pares the received data to the initial transmitted data
for verifying error free operation of the UART TX/RX
circuits. In this mode, the receiver, transmitter and
modem control interrupts are fully operational. How-
ever, the interrupts can only be read using lower four
bits of the Modem Control Register (MCR bits 0-3)
instead of the four Modem Status Register bits 4-7.
The interrupts are still controlled by the IER. Please
note that OP1# and OP2# pins are not brought out and
not available.
Rev. P1.00
23
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