XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
Preliminary
XR16C872
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the internal registers. UART A and B has same
register set independently control. The assigned bit functions are defined in the following paragraphs.
UART INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *3
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
Basic Registers are accessible when LCR bit-7 is set to logic 0. (Shaded bits are enabled by EFR bit-4)
0 0 0 RHR [XX] bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
000
001
010
010
011
100
THR [XX]
IER [00]
FCR [00]
ISR [01]
bit-7
bit-6
bit-5
bit-4
bit-3
11111111111112222222222222in3333333333333C4444444444444t5555555555555eT66666666666660r7777777777777S/r8888888888888u9999999999999#0000000000000p1111111111111t2222222222222 11111111111112222222222222in3333333333333R4444444444444t5555555555555eT66666666666660r7777777777777S/r8888888888888u9999999999999#0000000000000p1111111111111t2222222222222 1111111111111i2222222222222n33333333333334444444444444tXe555555555555506666666666666ro7777777777777/rf8888888888888uf9999999999999p00000000000001111111111111t22222222222223333333333333 11111111111112222222222222Sm33333333333334444444444444lo0e55555555555556666666666666/de7777777777777e8888888888888p999999999999900000000000001111111111111
modem
status
interrupt
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
111111111112222222222233333333333t(r44444444444M0i55555555555g/66666666666ST77777777777g88888888888XBe9999999999900000000000)r11111111111
11111111111t22222222222(r333333333330Li44444444444g/S55555555555Tg66666666666BX77777777777e88888888888)99999999999r0000000000011111111111
DMA
mode
select
0/
FIFO’s
enabled
0/
FIFO’s
enabled
111111111112222222222233333333333RC4444444444455555555555TT066666666666S77777777777S/88888888888##9999999999900000000000, 11111111111
111111111112222222222233333333333DX44444444444055555555555oe66666666666/ft77777777777f.88888888888999999999990000000000011111111111
int
priority
bit-2
bit-2
receive
line
status
interrupt
XMIT
FIFO
reset
int
priority
bit-1
bit-1
transmit
holding
register
RCVR
FIFO
reset
int
priority
bit-0
bit-0
receive
holding
register
FIFO
enable
int
status
LCR [00]
MCR [00]
divisor
set
set
latch break parity
enable
111111111122222222223333333333sC44444444445555555555el6666666666ol7777777777e8888888888cc9999999999k0000000000t11111111112222222222 111111111122222222223333333333e4444444444InR555555555566666666660aR7777777777/b8888888888T9999999999l0000000000e11111111112222222222 1111111111X22222222223333333333o44444444445555555555n06666666666-7777777777/A88888888889999999999n00000000001111111111y22222222223333333333
even
parity
loop
back
parity
stop
enable bits
(OP2#) (OP1#)
word
length
bit-1
RTS#
word
length
bit-0
DTR#
1 0 1 LSR [60]
0/
FIFO
error
trans. trans. break framing
shift reg. holding interrupt error
empty reg. empty
parity
error
overrun receive
error
data
ready
1 1 0 MSR [00]
1
1
1
1111111122222222SF33333333I44444444PF55555555R66666666O7777777788888888[99999999CF00000000F11111111o22222222u]3333333344444444on55555555rt6666666677777777
CD#
bit-7
RI#
bit-6
DSR# CTS#
bit-5
bit-4
delta
CD#
bit-3
delta
RI#
bit-2
delta
DSR#
bit-1
delta
CTS#
bit-0
Baud Rate Generator Registers are accessible only when LCR bit-7 is set to a logic 1.
0 0 0 DLL [XX] bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9
bit-8
Rev. P1.00
25
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