XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
XR16C872
Preliminary
Trigger Table-A (Transmit)
“Default setting after reset, ST16C550 mode”
BIT-5
BIT-4
FIFO Trigger Level
X
X
None
Trigger Table-B (Transmit)
BIT-5
0
0
1
1
BIT-4
0
1
0
1
FIFO Trigger Level
16
8
24
30
Trigger Table--C (Transmit)
BIT-5
BIT-4
FIFO Trigger Level
0
0
8
0
1
16
1
0
32
1
1
56
Trigger Table-D (Transmit)
BIT-5
BIT-4
FIFO trigger level
X
X
User programmable
trigger levels
FCR BIT 6-7: (logic 0 or cleared is the default condition,
RX trigger level =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The interrupt will trigger again
when RX data is unloaded below the threshold and
incoming data fills it back up to the trigger level. The
FCTR Bits 4-5 selects one of the following table.
Trigger Table-A (Receive)
“Default setting after reset, ST16C550 mode”
BIT-7
BIT-6
FIFO trigger level
0
0
1
0
1
4
1
0
8
1
1
14
Trigger Table-B (Receive)
BIT-7
BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
24
1
1
28
Trigger Table-C (Receive)
BIT-7
BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
56
1
1
60
Trigger Table-D (Receive)
BIT-7
BIT-6
FIFO trigger level
X
X
User programmable
trigger levels
Rev. P1.00
30
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