XRT7302IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IV' PDF : 62 Pages View PDF
XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.6
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PRELIMINARY
SYSTEM DESCRIPTION
A functional block diagram of the XRT7302 E3/DS3/
STS-1 Transceiver IC is presented in Figure 6. The
XRT7302 contains three independent transmitter and
receiver sections and a common microprocessor in-
terface section.
THE TRANSMIT SECTION - CHANNELS 0 AND 1
The Transmit Section of each Channel accepts TTL/
CMOS level signals from the Terminal Equipment in
either a Single-Rail or Dual-Rail format. The Transmit
Section takes this data and does the following:
• Encode this data into the B3ZS format if the DS3 or
SONET STS-1 Modes have been selected, or into
the HDB3 format if the E3 Mode has been selected.
• Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
• Drive these pulses onto the line via the TTIP(n) and
TRing(n) output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) onto
the line by driving either a positive or negative polarity pulse
across the 1:1 Transformer in a given bit period. The Trans-
mit Section drives a "0" (or a Space) onto the line by driving
no pulse onto the line.
THE RECEIVE SECTION - CHANNELS 0 AND 1
The Receive Section of each Channel receives a bi-
polar signal from the line via the RTIP and RRing sig-
nals across a 1:1 Transformer or a 0.01µF Capaci-
tor. The Receive Section will do the following:
• Adjust the signal level through an AGC circuit.
• Optionally equalize this signal for cable loss.
• Route the sliced data to the HDB3/B3ZS Decoder,
during which the original data content as transmit-
ted by the Remote Terminal Equipment is restored
to its original content.
• The recovered clock and data outputs to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS(n), RNEG(n) and RxClk(n) out-
put pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT7302 contains two identical channels. The
Microprocessor Interface Inputs are common to both
channels. The descriptions that follow refer to Chan-
nel(n) where (n) represents Channel0 or Channel1.
The XRT7302 can be configured to operate in either
the Hardware Mode or the HOST Mode.
a. Operating in the Hardware Mode
The XRT7302 can be configured to operate in the
Hardware Mode by tying the HOST/(HW) input pin to
GND.
When the XRT7302 is operating in the Hardware
Mode, the following is true:
1. The Microprocessor Serial Interface block is dis-
abled.
2. The XRT7302 is configured via input pin settings.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as de-
fined in Table 1.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL
INTERFACE PINS WHEN THE XRT7302 IS OPERATING IN
THE HARDWARE MODE
PIN #
PIN NAME
17 CS/(ENDECDIS)
18
SClk/(RxOFF1)
19
SDI/(RxOFF0)
20
SDO/(E3_Ch0)
42 REGR/(RxClkINV)
FUNCTION WHILE IN
HARDWARE MODE
ENDECDIS
RxOFF1
RxOFF0
E3_Ch0
RxClkINV
When the XRT7302 is operating in the Hardware
Mode, all of the remaining input pins become active.
b. Operating in the HOST Mode
The XRT7302 can be configured to operate in the
HOST Mode by tying the HOST/(HW) input pin to
VDD.
When the XRT7302 is operating in the HOST Mode,
the following is true:
1. The Microprocessor Serial Interface block is
enabled. Writing the appropriate data into the
on-chip Command Registers makes many config-
uration selections.
2. All of the following input pins are disabled and
should be connected to GND.
• Pins 1, 60 - TxLEV(n)
• Pins 2, 59 - TAOS(n)
• Pins 30, 31 - REQEN(n)
• Pins 25, 36 - RLB(n)
• Pins 24, 37 - LLB(n)
• Pin 39 - E3_Ch(n)
• Pins 21, 41 - STS1/DS3_Ch(n)
In HOST Mode Operation, the TxOFF(n) input pins
can still be used to turn on or turn off the Transmit
Output Drivers in Channels 0 and 1, respectively.
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