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PRELIMINARY
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.6
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(N) OF THE XRT7302, VIA THE E3_CH(N) AND STS-1/
DS3_CH(N) INPUT PINS (HARDWARE MODE)
DATA RATE
STATE OF E3_CH(N) PIN
(PIN 20 OR 39)
STATE OF STS-1/DS3_CH(N)
PIN
(PIN 21 OR 41)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
STS-1 (51.84 Mbps)
0
1
B3ZS
b. Operating in the HOST Mode.
To configure the Data Rate of a Channel, write the
appropriate values into the STS-1/DS3_Ch(n) and
E3_Ch(n) bit-fields in Command Register CR4-(n).
NOTE: Reference Table 2 for the correct address of each
channel.
COMMAND REGISTER CR4-(N)
D4
D3
D2
D1
D0
X STS-1/(DS3)_(n)) E3_Ch(n) LLB(n) RLB(n)
X
X
X
X
Xs
Table 4 relates the values of these two bit-fields to the
selected data rates.
TABLE 4: SELECTING THE DATA RATE FOR CHANNEL(N)
OF THE XRT7302 VIA THE STS-1/DS3_CH(N) AND THE
E3_CH(N) BIT-FIELDS IN THE APPROPRIATE COMMAND
REGISTER (HOST MODE)
SELECTED DATA STS-1/DS3_CH(N)
RATE
(D3)
E3
X (Don't Care)
DS3
0
STS-1
1
E3_CH(N)
(D2)
1
0
0
Making these selections does the following:
• Configure the VCO Center Frequency of Chan-
nel(n) of the Clock Recovery Phase-Locked Loop to
match the selected data rate.
• If the DS3 or STS-1 data rates are selected, it con-
figures the B3ZS/(HDB3) Encoder and Decoder
blocks to support B3ZS Encoding/Decoding.
• If the E3 data rate is selected, it configures the
B3ZS/(HDB3) Encoder and Decoder blocks to sup-
port HDB3 Encoding/Decoding.
• Configure the on-chip Pulse-Shaping circuitry to
generate Transmit Output pulses of the appropriate
shape and width to meet the applicable pulse tem-
plate requirement.
• Establishes the LOS Declaration/Clearance Criteria
for Channel(n) (Section 3.5).
2.0 THE TRANSMIT SECTION
Figure 6 shows the Transmit Section in each Channel
of the XRT7302 consists of the following blocks:
• Transmit Logic Block
• TxClk(n) Duty Cycle Adjust Block
• HDB3/(B3ZS) Encoder
• Pulse Shaping Block
The purpose of the Transmit Section in each Channel
of the XRT7302 is to take TTL/CMOS level data from
the Terminal Equipment and encode it into a format
that can:
1. be efficiently transmitted over coaxial cable at E3,
DS3 or STS-1 data rates,
2. be reliably received by the Remote Terminal
Equipment at the other end of the E3, DS3 or
STS-1 data link, and
3. comply with the applicable pulse template
requirements.
The circuitry that the Transmit Section in each Chan-
nel of the XRT7302 takes to accomplish this goal is
discussed below.
2.1 THE TRANSMIT LOGIC BLOCK
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single-Rail (binary data stream)
TTL/CMOS level data and timing information from the
Terminal Equipment.
2.1.1 Accepting Dual-Rail Data from the Termi-
nal Equipment
Whenever the XRT7302 accepts Dual-Rail data from
the Terminal Equipment, it does so via the following
input signals:
• TPData(n)
• TNData(n)
• TxClk(n)
Figure 7 illustrates the typical interface for the trans-
mission of data in a Dual-Rail Format between the
Terminal Equipment and the Transmit Section of the
XRT7302.
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