XRT7302IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IV' PDF : 62 Pages View PDF
áç
PRELIMINARY
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
The intent behind this feature is to permit a system
designed for redundancy to quickly switch out a de-
fective line card and switch-in the back-up line card.
FIGURE 6. FUNCTIONAL BLOCK DIAGRAM OF THE XRT7302
E3_Ch(n) STS-1/DS3_Ch(n) Host/(HW) RLOL(n) EXClk(n)
RxOFF
RxClkINV
XRT7302
REV. 1.1.6
RTIP(n)
RRing(n)
REQEN(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
TTIP(n)
TRing(n)
MTIP(n)
MRing(n)
DMO(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Data
Recovery
Serial
Processor
Interface
Loop MUX
Invert
HDB3/
B3ZS
Decoder
Device
Monitor
Pulse
Shaping
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Channel 0
Channel 1
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Notes: 1. (n) = 0 or 1 for the respective Channel
2. Serial Processor Interface input pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode.
1.0 SELECTING THE DATA RATE
Each channel in the XRT7302 can be configured to
support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or
SONET STS-1 (51.84 Mbps) rates and to operate in a
mode/data rate that is independent of the other chan-
nel.
Two methods are available to select the data rate for
each channel of the XRT7302.
1.1 CONFIGURING CHANNEL(N)
Refer to Table 2 to determine the appropriate
Address for each Command Register of each chan-
nel in the XRT7302. The Command Register
description refers to CR(m)-(n), where (m) = 0 to 7
and (n) refers to a particular channel of the
XRT7302.
23
Share Link: 
