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XRT7302IV View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
XRT7302IV
Exar
Exar Corporation Exar
'XRT7302IV' PDF : 62 Pages View PDF
XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.6
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PRELIMINARY
FIGURE 7. THE TYPICAL INTERFACE FOR DATA TRANSMISSION IN DUAL-RAIL FORMAT FROM
THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL OF THE
XRT7302
TxPOS
TPData
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
TxNEG
TxLineClk
TNData
TxClk
Transmit
Logic
Block
Exar E3/DS3/STS-1 LIU
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 8. The
Transmit Section of a Channel typically samples the
data on the TPData and TNData input pins on the fall-
ing edge of TxClk(n).
FIGURE 8. HOW THE XRT7302 SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
Data
TPData
TNData
TxClk
1
1
0
TxClk(n) is the clock signal that is of the selected data
rate frequency for E3 = 34.368 MHz, DS3 = 44.736
MHz and STS-1 = 51.84 MHz. If the Transmit Section
samples a “1" on the TPData input pin, the Transmit
Section of the XRT7302 generates a positive polarity
pulse via the TTIP(n) and TRing(n) output pins across
a 1:1 transformer. If the Transmit Section samples a
"1" on the TNData input pin, then the Transmit Sec-
tion ultimately generates a negative polarity pulse via
the TTIP(n) and TRing(n) output pins across a 1:1
transformer.
2.1.2 Configure Channel(n) to accept Single-
Rail Data from the Terminal Equipment
To transmit data in a Single-Rail data from the Termi-
nal Equipment, configure the XRT7302 in the HOST
Mode.
Write a "1" into the TxBin(n) (TRANSMIT BINary) bit-
field of Command Register CR1-(n) shown below.
NOTE: Please refer to Table 2 for the Address of the individ-
ual Channel(n).
COMMAND REGISTER CR1-(N)
D4
D3
D2
D1
D0
TxOFF(n) TAOS(n) TxClkINV(n) TxLEV(n) TxBin(n)
X
X
X
X
1
The Transmit Section of each channel samples this
input pin on the falling edge of the TxClk(n) clock sig-
nal and encodes this data into the appropriate bipolar
line signal across the TTIP(n) and TRing(n) output
pins.
NOTES:
26
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