XRT7302IV View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IV' PDF : 62 Pages View PDF
XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.6
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PRELIMINARY
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
TABLE 2: ADDRESSES AND BIT FORMATS OF XRT7302 COMMAND REGISTERS
REGISTER BIT-FORMAT
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
CHANNEL0
CR0-0
RO
RLOL0
RLOS0
ALOS0
DLOS0
CR1-0
R/W
TxOFF0
TAOS0
TxClkINV0 TxLEV0
CR2-0
R/W
Reserved ENDECDIS0 ALOSDIS0 DLOSDIS0
CR3-0
R/W
SR/(DR)_0 LOSMUT0
RxOFF0 RxClk0INV
CR4-0
R/W
Reserved STS-1/DS3_Ch0 E3_Ch0
LLB0
CR5-0
R/W
Reserved
Reserved
Reserved Reserved
CR6-0
R/W
Reserved
Reserved
Reserved Reserved
CR7-0
R/W
Reserved
Reserved
Reserved Reserved
CHANNEL1
CR0-1
RO
RLOL1
RLOS1
ALOS1
DLOS1
CR1-1
R/W
TxOFF1
TAOS1
TxClkINV1 TxLEV1
CR2-1
R/W
Reserved ENDECDIS1 ALOSDIS1 DLOSDIS1
CR3-1
R/W
SR/(DR)_1 LOSMUT1
RxOFF1 RxClk1INV
CR4-1
R/W
Reserved STS-1/DS3_Ch1 E3_Ch1
LLB1
CR5-1
R/W
Reserved
Reserved
Reserved Reserved
CR6-1
R/W
Reserved
Reserved
Reserved Reserved
CR7-1
R/W
Reserved
Reserved
Reserved Reserved
D0
DMO0
TxBIN0
REQEN0
Reserved
RLB0
Reserved
Reserved
Reserved
DMO1
TxBIN1
REQEN1
Reserved
RLB1
Reserved
Reserved
Reserved
Address:
The register addresses presented in the Hexadeci-
mal format.
Type:
The Command Registers are either Read-Only (RO)
or Read/Write (R/W) type of registers.
The default value for each of the bit-fields in these
registers is "0".
a. Operating in the Hardware Mode
To configure individual Channel Data Rate, set the
E3_Ch(n) and the STS-1/DS3_Ch(n) input pins
(where n = 0 or 1) to the appropriate logic states
referenced in Table 3.
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(N) OF THE XRT7302, VIA THE E3_CH(N) AND STS-1/
DS3_CH(N) INPUT PINS (HARDWARE MODE)
DATA RATE
STATE OF E3_CH(N) PIN
(PIN 20 OR 39)
STATE OF STS-1/DS3_CH(N)
PIN
(PIN 21 OR 41)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps)
1
X (Don't Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
24
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