XRT83SH38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SH38ES' PDF : 78 Pages View PDF
XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 2: MASTER CLOCK GENERATOR
MCLKE1
KHZ
MCLKT1
KHZ
CLKSEL2
CLKSEL1
CLKSEL0
16
x
0
1
1
16
x
0
1
1
56
x
1
0
0
56
x
1
0
0
64
x
1
0
1
64
x
1
0
1
128
x
1
1
0
128
x
1
1
0
256
x
1
1
1
256
x
1
1
1
REV. 1.0.7
MCLKRATE
0
1
0
1
0
1
0
1
0
1
MASTER CLOCK
KHZ
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
3.0 RECEIVE PATH LINE INTERFACE
The receive path of the XRT83SH38 LIU consists of 8 independent T1/E1/J1 receivers. The following section
describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified
block diagram of the receive path is shown in Figure 5.
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH
RCLK
RPOS
RNEG
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
3.1 Line Termination (RTIP/RRING)
3.1.1 CASE 1: Internal Termination
The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through
RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU.
This allows one bill of materials for all modes of operation reducing the number of external components
necessary in system design. The receive termination impedance is selected by programming TERSEL[1:0] to
match the line impedance. Selecting the internal impedance is shown in Table 3.
TABLE 3: SELECTING THE INTERNAL IMPEDANCE
TERSEL[1:0]
RECEIVE TERMINATION
0h (00)
100Ω
1h (01)
110Ω
2h (10)
75Ω
3h (11)
120Ω
21
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