XRT83SH38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SH38ES' PDF : 78 Pages View PDF
XRT83SH38
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
The XRT83SH38 has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL
is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also
available to control the receive termination for all channels simultaneously. This hardware pin takes priority
over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the
state of this pin is ignored. See Figure 6 for a typical connection diagram using the internal termination.
FIGURE 6. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT83SH38 LIU
RTIP
Receiver
Input
RRING
Internal Impedance
1:1
Line Interface T1/E1/J1
One Bill of Materials
3.1.2 CASE 2: Internal Termination With One External Fixed Resistor for All Modes
Along with the internal termination, a high precision external fixed resistor can be used to optimize the return
loss. This external resistor can be used for all modes of operation ensuring one bill of materials. There are
three resistor values that can be used by setting the RxRES[1:0] bits in the appropriate channel register.
Selecting the value for the external fixed resistor is shown in Table 4.
TABLE 4: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR
RXRES[1:0]
EXTERNAL FIXED RESISTOR
0h (00)
None
1h (01)
240Ω
2h (10)
210Ω
3h (11)
150Ω
By default, RxRES[1:0] is set to "None" for no external fixed resistor. If an external fixed resistor is used, the
XRT83SH38 uses the parallel combination of the external fixed resistor and the internal termination as the
input impedance. See Figure 7 for a typical connection diagram using the external fixed resistor.
NOTE: Without the external resistor, the XRT83SH38 meets all return loss specifications. This mode was created to add
flexibility for optimizing return loss by using a high precision external resistor.
FIGURE 7. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR
XRT83SH38 LIU
RTIP
Receiver
Input
RRING
Internal Impedance
1:1
R
Line Interface T1/E1/J1
R=240Ω, 210Ω, or 150Ω
3.2 Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
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