XRT83SH38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SH38ES' PDF : 78 Pages View PDF
XRT83SH38
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
according to the receiver loss of signal section in this datasheet. The test configuration for measuring the
receive sensitivity is shown in Figure 10.
FIGURE 10. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY
W&G ANT20
Network
Analyzer
Tx
Cable Loss
Rx
E1 = PRBS 215 - 1
T1 = PRBS 223 - 1
Rx
Flat Loss
XRT83SH38
External Loopback
14-Channel
Tx
Long Haul LIU
3.2.2 Interference Margin
The interference margin for the XRT83SH38 will be added when the first revision of silicon arrives. The test
configuration for measuring the interference margin is shown in Figure 11.
FIGURE 11. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN
E1 = 1,024kHz
T1 = 772kHz
Sinewave
Generator
E1 = PRBS 215 - 1
T1 = PRBS 223 - 1
W&G ANT20 Tx
Network
Analyzer
Rx
Flat Loss
Cable Loss
Rx
External Loopback
XRT83SH38
Tx
14-Channel LIU
3.2.3 General Alarm Detection and Interrupt Generation
The receive path detects RLOS, AIS, QRPD and FLS. These alarms can be individually masked to prevent the
alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be
set "High" in the appropriate global register. Any time a change in status occurs (it the alarms are enabled), the
interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the
INT pin will return "High". The status registers are Reset Upon Read (RUR). The interrupts are categorized in
a hierarchical process block. Figure is a simplified block diagram of the interrupt generation process.
NOTE: The interrupt pin is an open-drain output that requires a 10kΩ external pull-up resistor.
3.2.3.1 RLOS (Receiver Loss of Signal)
In T1 mode, RLOS is declared if an incoming signal has no transitions over a period of 175 +/-75 contiguous
pulse intervals. However, the XRT83SH38 LIU has a built in analog RLOS so that the user can be notified
when the amplitude of the incoming signal has been attenuated -9dB below the equalizer gain setting. For
example: In T1 or E1 short haul mode, the equalizer gain setting is 15dB. Once the input reaches an
amplitude of -24dB below nominal, the LIU will declare RLOS. The RLOS circuitry clears when the input
reaches +3dB relative to where it was declared. This +3dB value is a pre-determined hysteresis so that
transients will not cause the RLOS to clear. In E1 mode, RLOS is declared if an incoming signal has no
transitions for N consecutive pulse intervals, where 10≤N≤255. According to G.775, no transitions in E1 mode
is defined between -9dB and -35dB below nominal. Figure 12 is a simplified block diagram of the analog
RLOS function. Table 6 summarizes the analog RLOS values for the different equalizer gain settings.
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