xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL314
REV. 1.0.1
TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION
CHANNEL 0-13 (0X07H-0XD7H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used.
D6
FLSDET FIFO LIMIT STATUS DETECT
RO
0
The FLSDET is used to determine whether the receiver or trans-
mitter FIFO has reached its limit status. If both FIFOs reach their
limit capacity, this bit will be set to "1".
0 = Receive JA
1 = Transmit JA
D5
CLOS5 Cable Loss Indication
RO
0
D4
CLOS4 This 6-Bit binary word indicates the cable attenuation on the
D3
CLOS3 receiver inputs RTIP/RRING within ±1dB with Bit 5 being the MSB.
D2
CLOS2
D1
CLOS1
D0
CLOS0
TABLE 33: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION
CHANNEL 0-13 (0X08H-0XD8H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
X
0
D6
1SEG6 Arbitrary Pulse Generation
R/W
0
D5
1SEG5 The transmit output pulse is divided into 8 individual segments.
0
D4
1SEG4 This register is used to program the first segment which corre-
0
D3
1SEG3 sponds to the overshoot of the pulse amplitude. There are four
0
segments for the top portion of the pulse and four segments for the
D2
1SEG2 bottom portion of the pulse. Segment number 5 corresponds to
0
D1
1SEG1 the undershoot of the pulse. The MSB of each segment is the sign
0
D0
1SEG0 bit.
0
Bit 6 = 0 = Negative Direction
Bit 6 = 1 = Positive Direction
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