XRT83SL314
REV. 1.0.1
xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
GLOBAL REGISTER (0XE5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D4
Reserved This Register Bit is Not Used
R/W
0
D3
LCVCH3 Line Code Violation Counter Select
R/W
0
D2
LCVCH2 These bits are used to select which channel is to be addressed for
0
D1
LCVCH1 reading the contents in register 0xE8h. It is also used to address
0
D0
LCVCH0 the counter for a given channel when performing an update or
0
reset on a per channel basis. By default, Channel 0 is selected.
0000 = None
0001 = Channel 0
0010 = Channel 1
0011 = Channel 2
0100 = Channel 3
0101 = Channel 4
0110 = Channel 5
0111 = Channel 6
1000 = Channel 7
1001 = Channel 8
1010 = Channel 9
1011 = Channel 10
1100 = Channel 11
1101 = Channel 12
1110 = Channel 13
TABLE 47: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION
GLOBAL REGISTER (0XE6H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
R/W
0
D6
Reserved This Register Bit is Not Used
R/W
0
D5
Reserved This Register Bit is Not Used
R/W
0
D4
allRST LCV Counter Reset for All Channels
R/W
0
This bit is used to reset all internal LCV counters to their default
state 0000h. This bit must be set to "1" for 1µS.
0 = Normal Operation
1 = Resets all Counters
D3
allUPDATE LCV Counter Update for All Channels
R/W
0
This bit is used to latch the contents of all 14 counters into holding
registers so that the value of each counter can be read. The chan-
nel is addressed by using bits D[3:0] in register 0xE5h.
0 = Normal Operation
1 = Updates all Counters
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