XRT83SL314
REV. 1.0.1
xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
GLOBAL REGISTER (0XE2H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D6
RxTCNTL Receive Termination Select Control
R/W
0
This bit sets the LIU to control the RxTSEL function with either the
individual channel register bit or the global hardware pin.
0 = Control of the receive termination is set to the register bits
1 = Control of the receive termination is set to the hardware pin
D5
EQFLAG5 Equalizer Attenuation Flag
R/W
0
D4
EQFLAG4 EQFLAG[5:0] is used to generate an interrupt condition for an
0
D3
EQFLAG3 RLOS other than the default setting described in the datasheet. A
0
D2
EQFLAG2 desired value can be programmed into this register. If EQFLAGE
0
D1
EQFLAG1
is enabled in register 0x04h and if this 6-Bit binary word is equal to
the 6-Bit cable loss indicator, an interrupt will be generated.
0
D0
EQFLAG0
0
TABLE 44: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION
GLOBAL REGISTER (0XE3H)
BIT
NAME
FUNCTION
D7
Reserved This Register Bit is Not Used
D6
Reserved This Register Bit is Not Used
D5
Reserved This Register Bit is Not Used
D4
Reserved This Register Bit is Not Used
D3
SL1 Slicer Level Select
D2
SL0 00 = 50%
01 = 45%
10 = 55%
11 = 68%
D1
EQG1 Equalizer Gain Control
D0
EQG0 00 = Normal
01 = Reduce Gain by 1dB
10 = Reduce Gain by 3dB
11 = Normal
Register
Type
R/W
R/W
R/W
R/W
R/W
Default
Value
(HW reset)
0
0
0
0
0
0
R/W
0
65