XRT83SL314IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL314IB' PDF : 83 Pages View PDF
XRT83SL314
REV. 1.0.1
xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SR/DR Single Rail/Dual Rail Mode
R/W
0
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
D6
ATAOS Automatic Transmit All Ones
R/W
0
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condi-
tion does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
D5
RCLKE Receive Clock Data
R/W
0
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
D4
TCLKE Transmit Clock Data
R/W
0
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
D3
DATAP Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
R/W
0
D2
Reserved This Register Bit is Not Used
R/W
0
D1
GIE Global Interrupt Enable
R/W
0
The global interrupt enable is used to enable/disable all interrupt
activity for all 14 channels. This bit must be set "High" for the inter-
rupt pin to operate.
0 = Disable all interrupt generation
1 = Enable interrupt generation to the individual channel registers
D0
SRESET Software Reset
R/W
0
Writing a "1" to this bit for more than 10µS initiates a device reset
for all internal circuits except the microprocessor register bits. To
reset the registers to their default setting, use the Hardware Reset
pin (See the pin description for more details).
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