REV. 1.0.1
XRT84L38
OCTAL T1/E1/J1 FRAMER
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
WR
RD
ALE_AS
Blast
µPType [2:0]
Rdy/DTACK
Reset
DBEn
Clk
CS
INT
A[6:0]
Data[7:0]
ACK[1:0]
Req[1:0]
Microprocessor
Interface
&
Programmable
Registers
DMA
Interface
1.2 The Microprocessor Interface Block Signal
The Framer may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor, using data, address and control signals.
The local µP configures the Framer (into a desired operating mode) by writing data into specific addressable,
on-chip Read/Write registers, or on-chip RAM. The microprocessor interface provides the signals which are
required for a general purpose microprocessor to read or write data into these registers. The Microprocessor
Interface also supports polled and interrupt driven environments. These interface signals are described below
in Table 5, Table 6, and Table 7. The microprocessor interface can be configured to operate in the Motorola
Mode, the Intel mode, as well as other modes. When the Microprocessor Interface is operating in the Motorola
mode, some of the control signals function in a manner required by the Motorola 68000 family of
microprocessors. Likewise, when the Microprocessor Interface is operating in the Intel Mode, then these
Control Signals function in a manner as required by the Intel 80xx family of microprocessors.
Table 5 lists and describes those Microprocessor Interface signals whose role is constant across the two
modes. Table 6 describes the role of some of these signals when the Microprocessor Interface is operating in
the Intel Mode. Likewise, Table 7 describes the role of these signals when the Microprocessor Interface is
operating in the Motorola Mode.
TABLE 5: XRT84L38 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL
AND MOTOROLA MODES
PIN NAME
TYPE
DESCRIPTION
µPTYPE[2:0]
I Microprocessor Interface Mode Select Input pins
These three pins are used to specify the Microprocessor Mode that the Microprocessor Inter-
face will operate in. The relationship between the state of these three input pins, and the cor-
responding Microprocessor Mode is presented in Table 1.
D[7:0]
I/O Bi-Directional Data Bus for register Read or Write Operations.
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