XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
7. Next, the µC/µP should initiate the bus cycle by toggling the RD_DS (Data Strobe) input pin "Low". When
the Framer senses that the WR_R/W (R/W*) input pin is "High" and that the RD_DS (Data Strobe) input pin
has toggled "Low", it will enable the input drivers of the bi-directional data bus, D[7:0].
8. After waiting the appropriate time, for this newly placed data to settle on the bi-directional data bus (e.g.,
the Data Setup time) the Framer will assert the RDY_DTACK output signal “Low”.
9. After the µC/µP detects the RDY_DTACK signal (from the Framer), the µC/µP should toggle the RD_DS
input pin "High". This action accomplishes two things.
a. It latches the contents of the bi-directional data bus into the Microprocessor Interface block.
b. It terminates the Write cycle.
Figure 7 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals,
during a Motorola-type Programmed I/O Write Operation.
FIGURE 7. MOTOROLA µP INTERFACE SIGNAL DURING PROGRAMMED I/O WRITE OPERATION
ALE_AS
A[6:0]
CS
D[7:0]
RD
WR
RDY_DTACK
Address of target Register
Data to be Written
1.3.2.3
Burst Mode I/O for Data Access
Burst Mode I/O access is a much faster way to transfer data between the µC/µP and the Microprocessor
Interface (of the Framer), than Programmed I/O. The reason why Burst Mode I/O is faster is explained below.
Data is placed upon the Address Bus input pins A[6:0] only for the very first access, within a given burst
access. The remaining read or write operations (within this burst access) do not require the placement of the
Address Data on the Address Data Bus. As a consequence, the user does not have to wait through the
Address Setup and Hold times for each of these Read/Write operation, within the Burst Access.
It is important to note that there are some limitations associated with Burst Mode I/O Operations.
1. All cycles within the Burst Access, must be either all Read or all Write cycles. No mixing of Read and Write
cycles is permitted.
2. A Burst Access can only be used when Read or Write operations are to be employed over a contiguous
range of address locations, within the Framer.
3. The very first Read or Write cycle, within a burst access, must start at the lowest address value, of the
range of addresses to be accessed. Subsequent operations will automatically be incremented to the very
next higher address value.
Examples of Burst Mode I/O operations are presented below for read and write operations, with both Intel-type
and Motorola-type µC/µP.
1.3.2.3.1
Burst I/O Access: Intel Mode
41
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