XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
At the completion of this initial read cycle, the µC/µP has read in the contents of the first register or buffer
location (within the Framer) for this particular burst access operation. In order to illustrate how this burst I/O
cycle works, the byte (or word) of data, that is being read in Figure 12 has been labeled Valid Data at Offset =
0x00. This indicates that the µC/µP is reading the very first register (or buffer location) in this burst access.
1.3.2.3.2.1.2
Subsequent Read Operations
The procedure that the µC/µP must use to perform the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycle, as described in steps B.1 through B.3, below.
B.1 Without toggling the ALE_AS input pin (e.g., keeping it "High"), toggle the RD_DS (Data Strobe) input
pin "Low". This step accomplishes the following.
a. The Framer internally increments the latched address value (within the Microprocessor Interface circuitry).
b. The output drivers of the bi-directional data bus (D[7:0]) are enabled. At some time later, the register or
buffer location corresponding to the incremented latched address value will be driven onto the bi-direc-
tional data bus.
NOTE: In order to insure that the Framer will interpret this signal as being a Read signal, the µC/µP should keep the
WR_R/W input pin "High".
B.2 After some settling time, the data on the bi-directional data bus will stabilize and can be read by the
µC/µP. The Framer will indicate that this data is ready to be read by asserting the RDY_DTACK
(DTACK) signal “Low”.
B.3 After the µC/µP detects the RDY_DTACK signal (from the Framer), it terminates the Read cycle by
toggling the RD_DS (Data Strobe) input pin "High".
For subsequent read operations, within this burst cycle, the µC/µP simply repeats steps B.1 through B.3, as
illustrated in Figure 13.
FIGURE 13. MOTOROLA µP INTERFACE SIGNALS, DURING SUBSEQUENT READ OPERATIONS OF A BURST I/O CYCLE
ALE_AS
A[6:0]
Address of Initial Target Register (Offset = 0x00)
CS
D[7:0]
RD
Not Valid
Valid Data at
Offset = 0x01
Not Valid
Valid Data at
Offset = 0x02
WR
RDY_DTACK
1.3.2.3.2.1.3
Terminating Burst Access Operation
The Burst I/O Access will be terminated upon the falling edge of the ALE_AS input signal. At this point the
Framer will cease to internally increment the latched address value. Further, the µC/µP is now free to execute
either a Programmed I/O access or to start another Burst Access Operation with the Framer.
1.3.2.3.2.2
Write Burst Access: Motorola-Mode
Whenever a Motorola-type µC/µP wishes to write the contents of numerous registers or buffer locations over a
contiguous range of addresses, then it should do the following.
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