XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
1.3.2.3.1.2.2
The Subsequent Write Operations
The procedure that the µC/µP must use to perform the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as described in steps B.1 through B.3.
B.1 Without toggling the ALE_AS input pin (e.g., keeping it "Low"), apply the value of the next byte or word
(to be written into the Framer) to the bi-directional data bus pins, D[7:0].
B.2 Toggle the WR_R/W (Write Strobe) input pin "Low". This step accomplishes two things.
a. It enables the input drivers of the bi-directional data bus.
b. It causes the Framer to internally increment the value of the latched address.
B.3 After waiting the appropriate amount of settling time the data, in the internal data bus, will stabilize and
is ready to be latched into the Framer Microprocessor Interface block. At this point, the µC/µP should
latch the data into the Framer by toggling the WR_R/W input pin "High".
For subsequent write operations, within this burst I/O access, the µC/µP simply repeats steps B.1 through B.3,
as illustrated in Figure 11.
FIGURE 11. µP INTERFACE SIGNALS, DURING SUBSEQUENT WRITE OPERATIONS OF A BURST I/O CYCLE
ALE_AS
A[6:0]
Address of Initial Target Register (Offset = 0x00)
CS
D[7:0]
Data Written at Offset = 0x01
Data Written at Offset = 0x02
RD
WR
RDY_DTACK
1.3.2.3.1.2.3
Terminating the Burst I/O Access
Burst Access Operation will be terminated upon the rising edge of the ALE_AS input signal. At this point the
Framer will cease to internally increment the latched address value. Further, the µC/µP is now free to execute
either a Programmed I/O access or to start another Burst Access Operation with the XRT84L38 Framer.
1.3.2.3.2
Burst I/O Access: Motorola Mode
If the XRT84L38 Framer is interfaced to a Motorola-type µC/µP (e.g., the MC680x0 family, etc.), then it should
be configured to operate in the Motorola mode (by tying the MOTO pin to VCC). Motorola-type Read and Write
Burst I/O Access operations are described below.
1.3.2.3.2.1
Read Burst I/O Access Operation: Motorola-Mode
Whenever a Motorola-type µC/µP wishes to read the contents of numerous registers or buffer locations over a
contiguous range of addresses, then it should do the following.
a. Perform the initial Read operation of the burst access.
b. Perform the remaining read operations in the burst access.
c. Terminate the burst access operation.
Each of these operations, within the Burst Access are discussed below.
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