XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
Figure 8 presents an illustration of the behavior of the Microprocessor Interface Signals, during the initial Read
Operation, within a Burst I/O Cycle for an Intel-type µC/µP.
FIGURE 8. INTEL µP INTERFACE SIGNALS, DURING THE INITIAL READ OPERATION OF A BURST CYCLE
ALE_AS
A[6:0]
CS
D[7:0]
RD
WR
RDY_DTACK
Address of Initial Target Register (Offset = 0x00)
Not Valid
Valid Data of
Offset = 0x00
At the completion of this initial read cycle, the µC/µP has read in the contents of the first register or buffer
location (within the Framer) for this particular burst I/O access operation. In order to illustrate how this burst
access operation works, the byte (or word) of data, that is being read in Figure 8, has been labeled Valid Data
at Offset = 0x00. This label indicates that the µC/µP is reading the very first register (or buffer location) in this
burst access operation.
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