XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
Figure 14 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals,
during the Initial write operation within a Burst Access, for a Motorola-type µC/µP.
FIGURE 14. MOTOROLA µP INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF A BURST CYCLE
ALE_AS
A[6:0]
CS
D[7:0]
RD
WR
RDY_DTACK
Address of Initial Target Register (Offset = 0x00)
Data to be Written
(Offset = 0x00)
At the completion of this initial write cycle, the µC/µP has written a byte or word into the first register or buffer
location (within the Framer) for this particular burst I/O access. In order to illustrate how this burst I/O cycle
works, the byte (or word) of data, that is being written in Figure 14 has been labeled Data to be Written (Offset
= 0x00).
1.3.2.3.2.2.2
The Subsequent Write Operations
The procedure that the µC/µP must use to perform the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as described in steps B.1 through B.3.
B.1 Without toggling the ALE_AS input pin (e.g., keeping it "Low"), apply the value of the next byte or word
(to be written into the Framer) to the bi-directional data bus pins, D[7:0].
B.2 Toggle the WR_R/W (Write Strobe) input pin "Low". This step accomplishes two things.
a. It enables the input drivers of the bi-directional data bus.
b. It causes the Framer to internally increment the value of the latched address.
B.3 After waiting the appropriate amount of settling time the data, in the internal data bus, will stabilize and
is ready to be latched into the Framer Microprocessor Interface block. At this point, the µC/µP should
latch the data into the Framer by toggling the WR_R/W input pin "High".
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