XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
BIT NUMBER
BIT NAME
1-0
Transmit Timing Source
Select
REV. 1.0.1
BIT TYPE
BIT DESCRIPTION
R/W Transmit Timing Source Select:
These two READ/WRITE bit-fields permit the user to select the
timing source of Transmit section of the framer.
When the framer is operating at non-multiplexed mode, that is,
the Transmit Back-plane interface is operating at a clock rate of
2.048MHz for T1, these two READ/WRITE bit-fields also deter-
mine the direction of Single Frame Synchronization Pulse
(TxSync), Multi-frame Synchronization Pulse (TxMSync) and
Transmit Serial Clock Input (TxSerClk). When the framer is oper-
ating at other Back-plane mode, the Single Frame Synchroniza-
tion Pulse (TxSync), Multi-frame Synchronization Pulse
(TxMSync) and Transmit Serial Clock Input (TxSerClk) are all
inputs.
When these bits are set to 00:
The Recovered Receive Line Clock is the timing source of
Transmit section of the framer. When operating at the non-multi-
plexed 2.048MHz Back-plane Interface mode, the Single Frame
Synchronization Pulse (TxSync), Multi-frame Synchronization
Pulse (TxMSync) and Transmit Serial Clock Input (TxSerClk) are
all outputs. Upon losing of the Recovered Receiver Line Clock,
the OSCCLK Driven Divided clock is automatically chosen to be
the timing source of the Transmit section of the framer.
When these bits are set to 01:
The Transmit Serial Clock is the timing source of Transmit sec-
tion of the framer. When operating at the non-multiplexed
2.048MHz Back-plane Interface mode, the Single Frame Syn-
chronization Pulse (TxSync), Multi-frame Synchronization Pulse
(TxMSync) and Transmit Serial Clock Input (TxSerClk) are all
inputs.
When these bits are set to 10:
The OSCCLK Driven Divided clock is the timing source of Trans-
mit section of the framer. When operating at the non-multiplexed
2.048MHz Back-plane Interface mode, the Single Frame Syn-
chronization Pulse (TxSync), Multi-frame Synchronization Pulse
(TxMSync) and Transmit Serial Clock Input (TxSerClk) are all
outputs. Upon losing of the Recovered Receiver Line Clock, the
OSCCLK Driven Divided clock is automatically chosen to be the
timing source of the Transmit section of the framer.
When these bits are set to 11:
The Recovered Receive Line Clock is the timing source of
Transmit section of the framer. When operating at the non-multi-
plexed 2.048MHz Back-plane Interface mode, the Single Frame
Synchronization Pulse (TxSync), Multi-frame Synchronization
Pulse (TxMSync) and Transmit Serial Clock Input (TxSerClk) are
all outputs. Upon losing of the Recovered Receiver Line Clock,
the OSCCLK Driven Divided clock is automatically chosen to be
the timing source of the Transmit section of the framer.
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