XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
BIT NUMBER
BIT NAME
4
Clock Loss Detection
Enable
3-2
OSCCLK Frequency
Select
REV. 1.0.1
BIT TYPE
BIT DESCRIPTION
R/W Clock Loss Detection Enable:
This READ/WRITE bit-field permits the user to enable the Clock
Loss Detection logic for the framer when the Recovered Receive
Line Clock is used as transmit timing source of the framer.
When this bit is set to zero:
The framer disables the Clock Loss Detection logic.
When this bit is set to one:
The framer enables the Clock Loss Detection logic. If the Recov-
ered Receive Line Clock is used as transmit timing source of the
framer, and if clock recovered from the LIU is lost, the framer can
detect loss of the Recovered Receive Line Clock. Upon detect-
ing of this occurrence, the framer will automatically begin to use
the OSCCLK Driven Divided clock as transmit timing source until
the LIU is able to regain clock recovery.
NOTE: This bit-field is ignored if the TxSerClk or the OSCCLK
Driven Divided clock is chosen to be the timing source of
Transmit Section of the framer.
R/W OSCCLK Frequency Select:
These two READ/WRITE bit-fields permit the user to select inter-
nal clock dividing logic of the framer depending on the frequency
of incoming oscillator clock (OSCCLK). The frequency of internal
clock used by the framer should be 12.352MHz.
When these bits are set to 00:
The framer will internally divide the incoming OSCCLK by one.
Therefore, the external oscillator clock applied to the OSCCLK
pin should be 12.352MHz.
When these bits are set to 01:
The framer will internally divide the incoming OSCCLK by two.
Therefore, the external oscillator clock applied to the OSCCLK
pin should be 24.704MHz.
When these bits are set to 10:
The framer will internally divide the incoming OSCCLK by four.
Therefore, the external oscillator clock applied to the OSCCLK
pin should be 49.408MHz.
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