XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
1.3.2.3.1.1.2
Subsequent Read Operations
The procedure that the µC/µP must use to perform the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycles, as described in steps 1 through 3 below.
B.1 Without toggling the ALE_AS input pin (e.g., keeping it "Low"), toggle the RD_DS input pin "Low". This
step accomplishes the following.
a. The Framer will internally increments the latched address value (within the Microprocessor Interface circuitry).
b. The output drivers of the bi-directional data bus, D[7:0] are enabled. At some time later, the register or buffer location
corresponding to the incremented latched address value will be driven onto the bi-directional data bus.
B.2 Immediately after the Read Strobe pin toggles "Low" the Framer will toggle the RDY_DTACK (READY)
output pin "Low" to indicate its NOT READY status.
B.3 After some settling time, the data on the bi-directional data bus will stabilize and can be read by the
µC/µP. The Framer will indicate that this data is ready to be read by toggling the RDY_DTACK
(READY) signal "High".
B.4 After the µC/µP detects the RDY_DTACK signal (from the Framer), it can terminate the Read cycle by
toggling the RD_DS (Read Strobe) input pin "High".
For subsequent read operations, within this burst cycle, the µC/µP simply repeats steps 1 through 3, as
illustrated in Figure 9.
FIGURE 9. INTEL µP INTERFACE SIGNALS, DURING SUBSEQUENT READ OPERATIONS OF A BURST I/O CYCLE
ALE_AS
A[6:0]
CS
D[7:0]
RD
WR
RDY_DTACK
Address of Initial Target Register (Offset = 0x00)
Not
Valid
Valid Data at
Offset = 0x01
Not
Valid
Valid Data at
Offset = 0x02
In addition to the behavior of the Microprocessor Interface signals, Figure 9 also illustrates other points
regarding the Burst Access Operation.
a. The Framer internally increments the address value, from the original latched value shown in Figure 8.
This is illustrated by the data, appearing on the data bus, (for the first read access) being labeled Valid
Data at Offset = 0x01 and that for the second read access being labeled Valid Data at Offset = 0x02.
b. The Framer performs this address incrementing process even though there are no changes in the Address
Bus Data, A[6:0].
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