XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
1.3.2.3.2.1.1
Initial Read Operation: Motorola Mode
The initial read operation of a Motorola-type read burst access is accomplished by executing a Programmed I/
O Read cycle, as summarized below.
A.0 Execute a Single Ordinary (Programmed I/O) Read Cycle, as described in steps A.1 through A.8
below.
A.1 Assert the ALE_AS (AS) input pin by toggling it "Low". This step enables the Address Bus input drivers
(within the Framer) within the Framer Microprocessor Interface Block.
A.2 Place the address of the initial target register or buffer location (within the Framer), on the Address Bus
input pins, A[6:0].
A.3 At the same time, the Address-Decoding circuitry (within the user's system) should assert the CS (Chip
Select) input pins of the Framer by toggling it "Low". This action enables further communication
between the µC/µP and the Framer Microprocessor Interface block.
A.4 After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Setup
time), the µC/µP should toggle the ALE_AS input pin "High". This step causes the Framer to latch the
contents of the Address Bus into its internal circuitry. At this point, the initial address of the burst
access has now been selected.
A.5 Further, the µC/µP should indicate that this cycle is a Read cycle by setting the WR_R/W (R/W) input
pin "High".
A.6 Next the µC/µP should initiate the current bus cycle by toggling the RD_DS (Data Strobe) input pin
"Low". This step will enable the bi-directional data bus output drivers, within the Framer. At this point,
the bi-directional data bus output drivers will proceed to driver the contents of the Address register
onto the bi-directional data bus.
A.7 After some settling time, the data on the bi-directional data bus will stabilize and can be read by the
µC/µP. The Framer will indicate that this data can be read by asserting the RDY_DTACK (DTACK)
signal “Low”.
A.8 After the µC/µP detects the RDY_DTACK signal (from the Framer) it will terminate the Read Cycle by
toggling the RD_DS (Data Strobe) input pin "High".
Figure 12 presents an illustration of the behavior of the Microprocessor Interface Signals during the initial
Read Operation, within a Burst I/O Cycle, for a Motorola-type µC/µP.
FIGURE 12. MOTOROLA µP INTERFACE SIGNALS DURING THE INITIAL READ OPERATION OF A BURST CYCLE
ALE_AS
A[6:0]
CS
D[7:0]
RD
WR
RDY_DTACK
Address of Initial Target Register (Offset = 0x00)
Not Valid
Valid Data at
Offset = 0x00
48
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