XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
Figure 10 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals,
during the initial write operation within a Burst Access, for an Intel-type µC/µP.
FIGURE 10. INTEL µP INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF A BURST CYCLE
ALE_AS
A[6:0]
CS
D[7:0]
RD
WR
RDY_DTACK
Address of Initial Target Register (Offset = 0x00)
Data to be Written
(Offset = 0x00)
At the completion of this initial write cycle, the µC/µP has written a byte or word into the first register or buffer
location (within the Framer) for this particular burst access operation. In order to illustrate this point, the byte (or
word) of data, that is being written in Figure 10 has been labeled Data to be Written (Offset = 0x00).
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