XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
TABLE 5: XRT84L38 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL
AND MOTOROLA MODES
PIN NAME
TYPE
DESCRIPTION
A[6:0]
I Seven-Bit Address Bus Inputs
The XRT84L38 Framer Microprocessor Interface uses a Multiplexed Address bus. This
address bus is provided to permit the user to select an on-chip register or buffer location for
Read/Write access.
CS
I Chip Select Input
This active-low signal selects the Microprocessor Interface of the XRT84L38 Framer and
enables Read/Write operations with the on-chip registers/buffer locations.
TABLE 6: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT84L38
INTEL
TYPE
PIN NAME EQUIVALENT PIN
DESCRIPTION
ALE_AS
ALE
I Address-Latch Enable: This active-high signal is used to latch the contents on
the address bus, A[6:0]. The contents of the Address Bus are latched into the
A[6:0] inputs on the falling edge of ALE_AS. Additionally, this signal can be
used to indicate the start of a burst cycle.
RD
RD*
I Read Signal: This active-low input functions as the read signal from the local µP.
When this signal goes "Low", the Framer Microprocessor Interface places the
contents of the addressed register on the Data Bus pins, D[7:0]. The Data Bus is
tri-stated once this input signal returns "High".
WR
WR*
I Write Signal: This active-low input functions as the write signal from the local
µP. The contents of the Data Bus (D[7:0]) is written into the addressed register
via A[6:0], on the rising edge of this signal.
RDY_DTAC
K
READY*
O Ready Output: This active-low signal is provided by the Framer and indicates
that the current read or write cycle is to be extended until this signal is asserted.
The local µP typically inserts WAIT states until this signal is asserted. This output
toggles "Low" when the device is ready for the next Read or Write cycle.
TABLE 7: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT84L38 MOTOROLA
TYPE
PIN NAME EQUIVALENT PIN
DESCRIPTION
ALE_AS
AS*
I Address Strobe: This active-low signal is used to latch the contents on the
address bus input pins, A[6:0], into the Microprocessor Interface circuitry. The
contents of the Address Bus are latched into the Framer on the rising edge of the
ALE_AS signal. This signal can also be used to indicate the start of a burst cycle.
RD
DS*
I Data Strobe: This signal latches the contents of the bi-directional data bus pins
into the Addressed Register within the Framer during a Write Cycle.
WR
R/W*
I Read/Write Input: When this pin is "High", it indicates a Read Cycle. When this
pin is "Low", it indicates a Write cycle.
RDY_DTAC
K
DTACK*
O Data Transfer Acknowledge: The Framer asserts DTACK in order to inform the
CPU that the present READ or WRITE cycle is nearly complete. The 68000 fam-
ily of CPUs requires this signal from its peripheral devices in order to quickly and
properly complete a READ or WRITE cycle.
1.3 Interfacing the XRT84L38 to the Local µC/µP via the Microprocessor Interface Block
36
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