XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
BIT NUMBER
BIT NAME
1-0
Alarm Indication Signal
Detection Select
REV. 1.0.1
BIT TYPE
BIT DESCRIPTION
R/W Alarm Indication Signal Detection Select:
These READ/WRITE bit-fields activate and de-activate Alarm
Indication Signal Detection of the framer.
When these bits are set to 00:
The framer disables detection of AIS Alarm.
When these bits are set to 01:
The framer enables detection of unframed AIS Alarm.
When these bits are set to 10:
The framer enables detection of AIS16 Alarm.
When these bits are set to 11:
The framer enables detection of framed AIS Alarm.
Synchronization Mux Register (SMR) - T1 Mode (Indirect Address = 0xn0H, 0x09H)
BIT 7
BIT 6
BIT 5
BIT 4
BIT3
BIT 2
BIT 1
Reserved
Transmit
Multi-frame
Alignment
Transmit
Super-frame
Synchroniza-
tion
Synchroniza-
tion Signal
Direction
Reserved
Reserved
CRC-6
Source
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
Framing Bit
Source
R/W
0
BIT NUMBER
BIT NAME
7
Reserved
6
Transmit Multi-frame
Alignment
BIT TYPE
BIT DESCRIPTION
R/W
R/W Transmit Multi-frame Alignment:
This READ/WRITE bit-field forces the framer to align the Trans-
mit Multi-frame boundary with the back-plane Multi-frame Syn-
chronization Pulse.
When this bit is set to zero:
The Transmit Multi-frame boundary is not aligned with the back-
plane Multi-frame Synchronization Pulse.
When this bit is set to one:
The Transmit Multi-frame boundary is forced to align with the
back-plane Multi-frame Synchronization Pulse.
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