XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
REV. 1.0.1
BIT NUMBER
BIT NAME
5
Transmit Super-frame
Synchronization
4
Synchronization Signal
Direction
3-2
Reserved
1
CRC-6 Source
XRT84L38
OCTAL T1/E1/J1 FRAMER
BIT TYPE
BIT DESCRIPTION
R/W Transmit Super-frame Synchronization:
This READ/WRITE bit-field determines the transmit synchroniza-
tion input signal (TxSync) being either the Frame Synchroniza-
tion signal or the Multi-frame Synchronization signal.
When this bit is set to zero:
The transmit synchronization input signal (TxSync) is the Frame
Synchronization signal that indicates the frame boundary. In
1.544Mbit/s basic mode, the Transmit Multi-frame Synchroniza-
tion input signal (TxMSync) indicates the Multi-frame boundary.
In other back-plane modes, the TxMSync input is an input trans-
mit clock.
When this bit is set to one:
The transmit synchronization input signal (TxSync) is the Trans-
mit Multi-frame Synchronization signal indicating the multi-frame
boundary.
R/W Synchronization Signal Direction:
This READ/WRITE bit-field determines the direction of transmit
synchronization signal (TxSync_n) and the Transmit Multi-frame
Synchronization signal (TxMSync_n). In H.100 interface mode,
this READ/WRITE bit-field determines the location of the trans-
mit synchronization pulse.
When this bit is set to zero:
The transmit synchronization signal is input if the Transmit Line
Clock Source Select bits of Clock Select Register (CSR) equal to
one. If the Transmit Line Clock Source Select bits of Clock
Select Register (CSR) is not equal to one, the transmit synchro-
nization signal is output.
In H.100 interface mode, the transmit synchronization pulse
occurs at the last and the first clock cycles of each frame.
When this bit is set to one:
The transmit synchronization signal is output if the Transmit Line
Clock Source Select bits of Clock Select Register (CSR) equal to
one. If the Transmit Line Clock Source Select bits of Clock
Select Register (CSR) is not equal to one, the transmit synchro-
nization signal is input.
In H.100 interface mode, the transmit synchronization pulse
occurs at the first two clock cycles of each frame.
R/W
R/W CRC-6 Source:
This READ/WRITE bit-field permits the user to determine where
the CRC-6 bits should be inserted.
When this bit is zero:
The CRC-6 bits are generated and inserted by the framer inter-
nally.
When this bit is one:
If the framer is operating in normal 1.544Mbit/s mode, the CRC-6
bits are passed through from the Transmit Serial Data input
(TxSer_n).
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