XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
1.3 Reference Clock Input
The XRT91L34 can accept either a 19.44 MHz or 77.76 MHz Differential clock input at REFCLKP/N or a
Single-Ended LVTTL clock input at TTLREFCLK. The REFCLKP/N or TTLREFCLK should be generated from
a source which has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to
have the necessary accuracy required for SONET systems. The reference clock can be provided with one of
two frequencies chosen by CDRREFSEL. The reference frequency options for the XRT91L34 are listed in
Table 2. Figure 3 illustrate the reference clock design options.
TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS)
CDRREFSEL
0
1
REFCLKP/N OR TTLREFCLK
FREQUENCY
77.76 MHz
19.44 MHz
CHANNEL 0 - 3
AVAILABLE DATA RATES
STS-1/STM-0 51.84 Mbps
STS-3/STM-1 155.52 Mbps
STS-12/STM-4 622.08 Mbps
FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS
Differential LVPECL or LVDS
Reference Clock Option
REFCLKP and REFCLKN pins
internally biased and terminated with
100 Ohm line-to-line
Differential Clock
Source
77.76/19.44 MHz
Resistors for LVPECL
Remove for LVDS
REFCLKP
REFCLKN
130 Ohm
100 VBB1.2
Internal
REFCLK
Tie unused TTLREFCLK
input pin to GND
TTLREFCLK
XRT91L34
Single-Ended LVTTL/LVCMOS
Reference Clock Option
Leave REFCLKP unconnected
and
tie REFCLKN pin to GND
REFCLKP
REFCLKN
100 VBB1.2
TTLREFCLK
Single Ended
Clock Source
77.76/19.44 MHz
Internal
REFCLK
XRT91L34
13
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