XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
2.0 RECEIVE SECTION
The receive section of XRT91L34 includes four differential input buffers RXDI[3:0]P/N, followed by clock and
data recovery units (CDR) and recovered serial data and clock differential output drivers. The receiver accepts
the high speed Non-Return to Zero (NRZ) serial data at 622.08/155.52/51.84 Mbps through the input interfaces
RXDI[3:0]P/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming data
stream. The recovered serial data is presented to the RXDO[3:0]P/N differential output driver interface. The
high-speed recovered clock RXCLKO[3:0]P/N, is used to synchronize the transfer of the RXDO[3:0]P/N data
with the receive portion of a framer/mapper device. The recovered data RXDO[3:0]P/N and clock
RXCLKO[3:0]P/N differential output driver interfaces are designed for ultimate flexibility by supporting either
LVDS or Differential LVPECL protocol level. Upon initialization or loss of signal or loss of lock, the external
reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock recovery phase-locked loop for
proper operation. The included CDR blocks in the XRT91L34 can be individually disabled by asserting the
CDRDIS[3:0] pins to permit the flexibility of powering down unused channels.
2.1 Receive Serial Input
The receive serial inputs are applied to RXDI[3:0]P/N. The XRT91L34 includes internal termination, this has
the advantage of reducing the number of external board components. The XRT91L34 terminates the receive
inputs using 100Ω line-to-line method of termination. Differential LVPECL operation of receive inputs can be
supported, provided each optical module Differential LVPECL output pin must have a 130Ω DC current path
resistor to GND whether internally or externally. A simplified LVDS/Differential LVPECL DC coupling block
diagram is shown in Figure 4.
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM
VBB1.2 100
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
VBB1.2 100
VBB1.2 100
VBB1.2 100
Internal 100 Ohm line-to-line
termination active on
RXDI[3:0]P and RXDI[3:0]N pins
RXDI0P
LVDS or DIFF LVPECL Operation
Internal 130 Ohm line to GND DC current path resistors
required for Optical Module DIFF LVPECL Operation
RXDI0N
Channel 0 Optical Module
Optical Fiber
RXDI1P
RXDI1N
Channel 1 Optical Module
Optical Fiber
RXDI2P
RXDI2N
Channel 2 Optical Module
Optical Fiber
RXDI3P
RXDI3N
Channel 3 Optical Module
Optical Fiber
NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.
AC or DC coupling is largely specific to system design and optical module of choice.
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